The GOA (Gate Driver on Array) technology, i.e. the array substrate row driving technology is to utilize the array manufacture process of the Thin Film Transistor (TFT) liquid crystal display to manufacture the gate driving circuit on the Thin Film Transistor array substrate for realizing the driving way of scanning the gates row by row. It possesses advantages of reducing the production cost and realizing the panel narrow frame design, and is utilized by many kinds of displays. The GOA circuit has two basic functions: the first is to output the scan driving circuit for driving the gate lines in the panel to activate the TFTs in the display areas and to charge the pixels; the second is the shift register function. When the output of one scan driving signal is accomplished, the output of the next scan driving signal is performed with the control of the clock signal, and the transfer carries on in sequence.
The embedded touch control technology is to combine the touch control panel and the display panel as one, and to merge the function of the touch control panel into the liquid crystal panel to make the liquid crystal panel equipped with functions of display and sensing the touch control inputs at the same time. With the rapid development of the display technology, the touch control display panel has been widely applied and accepted, used by the people. For example, the smart phone, the flat panel computer and etc. all use the touch control display panel.
The present embedded touch control technology can be categorized into two types: one is that the touch control circuit is on the liquid crystal cell (On Cell), and the other is that the touch control circuit is inside the liquid crystal cell (In Cell).
The In Cell touch display panel according to prior art performs function of sensing after the normal display is completed in each frame of image. Namely, the touch scan signal is on after all the respective GOA units of the GOA circuit accomplish outputting the gate scan driving signals to start sensing.
FIG. 1 shows a GOA circuit applied for an In Cell type touch display panel, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a forward-backward scan control module 100, a control input module 200, a reset module 300, a latch module 400, a NAND gate signal process module 500 and an output buffer module 600.
The forward-backward scan control module 100 is employed to select the stage transfer signals of the former, latter stages to realize the forward or backward scan driving. The control input module 200 is employed to control the input of the stage transfer signal to achieve the charge to the first node Q(N). The reset module 300 is employed to perform clear zero process to the first node Q(N). The latch module 400 is employed to latch the stage transfer signal. The NAND gate signal process module 500 is employed to NAND process to the latched stage transfer signal and clock signal to generate the gate scan driving signal of the stage; the output buffer module 600 comprises inverters of odd numbers in series, which are employed to enhance the driving ability of the gate scan driving signal to reduce the RC Loading.
Specifically, N is set to be a positive integer, and except the GOA unit of the first stage and the GOA unit of the last stage, in the GOA unit of the Nth stage:
the forward-backward scan control module 100 comprises: a first transmission gate TG1, and a low voltage level control end of the first transmission gate TG1 receives a first direct current control signal U2D, and a high voltage level control end receives a second direct current control signal D2U, and an input end is electrically coupled to a first node Q(N−1) of the former N−1th GOA unit, and an output end is electrically coupled to an input end of a first clock control inverter TF1; and a second transmission gate TG2, and a high voltage level control end of the second transmission gate TG2 receives the first direct current control signal U2D, and a low voltage level control end receives the second direct current control signal D2U, and an input end is electrically coupled to a first node Q(N+1) of the latter N+1th GOA unit, and an output end is electrically coupled to the input end of a first clock control inverter TF1; a voltage level of the first node Q(N−1) of the former N−1th GOA unit is employed to be a forward scan stage transfer signal, and a voltage level of the first node Q(N+1) of the latter N+1th GOA unit is employed to be a backward scan stage transfer signal;
the control input module 200 comprises: a first clock control inverter TF1, and a high voltage level control end of the first clock control inverter TF1 is electrically coupled to a Mth clock signal CK(M), and a low voltage level control end is electrically coupled to a Mth inverted clock signal XCK(M), and an output end is electrically coupled to a second node P(N);
the reset module 300 comprises: a first P-type thin film transistor T1, and a gate of the first P-type thin film transistor T1 receives a reset signal Reset, and a source receives a constant high voltage level VGH, and a drain is electrically coupled to the second node P(N);
the latch module 400 comprises: a second clock control inverter TF2, and a low voltage level control end of the second clock control inverter TF2 is electrically coupled to the Mth clock signal CK(M), and a high voltage level control end is electrically coupled to the Mth inverted clock signal XCK(M), and an input end is electrically coupled to the first node Q(N), and an output end is electrically coupled to the second node P(N); and a first inverter IN1, and an input end of the first inverter IN1 is electrically coupled to the second node P(N), and an output end is electrically coupled to the first node Q(N);
the NAND gate signal process module 500 comprises: a NAND gate NAND, and a first input end of the NAND gate NAND is electrically coupled to the first node Q(N), and a second input end receives a M+2th clock signal, and an output end is electrically coupled to an input end of a second inverter IN2;
the output buffer module 600 comprises: the second inverter IN2, and an output end of the second inverter IN2 is electrically coupled to an input end of the third inverter IN3; the third inverter IN3, and an output end of the third inverter IN3 is electrically coupled to an input end of a fourth inverter IN4; and the fourth inverter IN4, an output end of the fourth inverter IN4 is electrically coupled to a gate scan driving signal output end Gate(N).
The working process of the GOA circuit applied for an In Cell type touch display panel according to prior art in the normal display stage is: the forward scan is illustrated, and as the voltage level of the first node Q(N−1) of the former N−1th GOA unit is high, the Mth clock signal CK(M) provides high voltage level, and the first node Q(N) is charged to be high voltage level; after the Mth clock signal CK(M) is changed to be low voltage level, the first node Q(N) is latched by the latch module 300, and as the high voltage level of the M+2th clock signal CK(M+2) comes, the gate scan driving signal output end Gate(N) outputs high voltage level; after the M+2th clock signal CK(M+2) is changed to be low voltage level, the gate scan driving signal output end Gate(N) steadily outputs low voltage level.
However, in the touch scan stage, all the signal lines are overlapped with a pulse changing along with the touch driving signal. After the normal display of the touch display panel is finished, the touch scan is performed, the gate scan driving signal output end Gate(N) receives the constant low voltage level, and then the constant low voltage level changes along with the jump and change of the touch driving signal, and the gate scan driving signal also changes along the change of the touch driving signal. Such work of the touch scan panel requires performing waveform process to the gate scan driving signal in the touch scan stage with the Integrated Circuit (IC), and results in larger loading of the IC.